1. Field
At least one embodiment of the present invention pertains to identifying and correcting errors in data stored in a memory device having a host bus interface to allow access to the memory device by a host.
2. Background
Electrically operated machines, such as general-purpose and special-purpose computing devices (e.g., “computers”), data storage devices or systems, network servers, file servers, and Internet servers typically include computer processors and other devices (often operating under the control of a processor) that frequently need to store information in, or retrieve information from a computer memory.
For example, data storage device, such as a network server, file server, or Internet server to store data for access by other entities, such as client devices, may include various types of memory. The data storage device may include a “storage memory” having a number of mass storage devices, such as disk drives. The storage memory may be a storage subsystem located locally or remotely from the data storage device. Reading data from the drives and writing data to the drives can be controlled by an operating system and use a random access memory (RAM) type “main memory”.
The processors of the data storage device may have direct access to the main memory via an address and data bus connection or interface. As part of the main memory, the data storage device may include a cache memory to store data that is frequently or recently used when reading data from the drives and writing data to the drives.
For example, a data storage device, may be a server or a storage server having a storage memory, a main memory, and a cache memory to store and retrieve data on behalf of one or more client processing systems (clients). The cache memory may be part of the main memory and may be used to provide quick read and write access to data frequently or recently used (e.g., access without reading the data from storage memory). When data in the cache memory is going to be deleted or written over, a “victim cache” memory may be used to continue to store in the main memory (e.g., for access without reading the “victim” data from storage memory) the “victim” data to be deleted or written over. When the victim cache becomes full, data in the victim cache will also need to be deleted or written over. Thus, access to data deleted or written over in the victim cache will again require accessing the copy of that data in storage memory.
Depending on the size of and frequency of access to the storage memory and main memory, a larger maximum data storage size for the victim cache memory may be desired for peak performance. However, due to maximum data storage size for the hardware constrains of the device, it may not be possible to increase the size of the victim cache memory. In addition, when it is possible to increase the maximum data storage size for the victim cache memory, the increased size may result in an increased number of data errors due to the increased data stored therein. Moreover, as the number of errors increase, a single bit error in a portion of data stored in the victim cache memory may become a double bit error prior to that portion of data being read. Although single bit errors may be correctable, double bit errors may be difficult, if not impossible, to correct. Thus, in addition to increasing a data storage size of the victim cache, it may also be desirable to correct single bit errors in portions of data stored in the cache memory before they become double bit errors.